The present invention relates to a timing adjustment method and apparatus, which adjust the timing of various test signals in semiconductor IC testers.
In semiconductor IC testers, a method described in Japanese Patent Laid-Open 1992-127073 is conventionally known for adjusting the timing of signals supplied to drivers and comparators contained in tester pins. FIG. 2 shows the outline of this conventional technology.
With this conventional technology, a special IC (short-circuit chip 2), in which each signal pin is connected to each other, is replaced with a device under test, such as IC memory, and is connected with a semiconductor IC tester (IC tester 3). A control circuit 20 operates a timing generator 11. The timing generator 11 makes all drivers 21-2n, except a driver contained in a tester pin being adjusted, supply their outputs to the short-circuit chip 2. For example, when the tester pin containing the driver 21 is being adjusted, output signals from the drivers 22-2n contained in the tester pins other than the above-noted tester pin are supplied to the short-circuit chip 2. These output signals are compounded at a short-circuit terminal of the short-circuit chip 2 and turn into a single composite waveform. The control circuit 20 increases/decreases the amount of the delay time of a variable delay circuit 61 dedicated comparator based on this composite waveform, and adjusts the timing of the strobe signal supplied to comparators 31 and 41. By changing the tester pin being adjusted one by one, the above-mentioned timing adjustment process is performed on the comparators 31-3n and 41-4n contained in all tester pins.
After finishing this timing adjustment, with the output terminals of the tester pins being open or the short-circuit chip 2 being connected, the control circuit 20 increases/decreases the amount of the delay time of variable delay circuits 51-5n dedicated to driver based on the timing of the comparators 31-3n and 41-4n contained in each tester pin respectively, and adjusts the timing of the signals supplied to the drivers 21-2n. 
The above-mentioned timing adjustment to the comparators 31-3n and 41-4n is called a xe2x80x9csignal judgment system deskewxe2x80x9d, and the above-mentioned timing adjustment to the drivers 21-2n is called a xe2x80x9csignal supply system deskewxe2x80x9d. Conventionally, the signal supply system deskew is carried out after carrying out the signal judgment system deskew.
According to the timing adjustment method in the above-mentioned conventional technology, the signal judgment system deskew and the signal supply system deskew are available only for logic testers whose tester pins comprise the drivers 21-2n, the comparators 31-3n, 41-4n and I/O switches 71-7n that connect the drivers and the comparators, or for completely par pin type testers. Therefore, the above-mentioned timing adjustment is not able to be performed on memory testers having only drive-only tester pins.
The present invention is made in view of the above problem. The purpose of the present invention is to offer a timing adjustment method and apparatus, which can perform timing adjustment by carrying out the signal judgment system deskew and the signal supply system deskew even if a semiconductor IC tester has two or more drive-only tester pins.
According to the present invention, the features of a timing adjustment method for a semiconductor IC tester, which has a plurality of drive-only pins, includes a first step of connecting at least one comparator and an output end of each driver through a switch, one by one, and carrying out the signal judgment system deskew on each drive-only pin. A second step connects the comparator and an output end of each driver through the switches, one by one, and carries out the signal supply system deskew on each drive-only pin according to the result of the signal judgment system deskew.
According to the present invention, the features of a timing adjustment apparatus for a semiconductor IC tester, which has a plurality of drive-only pins, includes a switch connected with an output end of each driver contained in a plurality of drive-only pins, at least one comparator connected in common with the plurality of drivers through the switches, and a control circuit for changing the switches, one by one, and carrying out the signal judgment system deskew on the drive-only pin, which is connected with the comparator, and for changing the switches, one by one, and carrying out the signal supply system deskew on the drive-only pin, which is connected with the comparator, according to the result of the signal judgment system deskew.
In the present invention, the comparator is connected with two or more drive-only pins through the switches, and the comparator is shared by two or more drive-only pins by changing the switches. The switches are changed one by one, and the signal judgment system deskew is carried out on the drive-only pin, which is connected with the comparator. After that, the switches are changed one by one, and the signal supply system deskew is carried out on the drive-only pin, which is connected with the comparator, based on the result of the signal judgment system deskew. Therefore, the timing adjustment by the signal judgment system deskew and the signal supply system deskew can be performed also on the drive-only pins.